1. Field of the Invention
This invention relates generally to the field of semiconductor circuit design, and more particularly to the design of a capacitor structure on a semiconductor substrate.
2. Description of the Related Art
Many integrated circuits (ICs), including mixed-signal circuits that include both digital and analog components, oftentimes require high-performance capacitors configured on the chip. Currently, a wide variety of applications—for example dynamic random access memories, phase-locked loops, voltage controlled oscillators, operational amplifiers, and switched capacitor circuits—feature capacitors formed on integrated circuits. Generally, these on-chip capacitors can also be used to decouple digital and analog integrated circuits from potential noise that may be generated by the rest of the system. In many of the present systems, on-chip capacitors are designed as metal-to-metal capacitors due to the advantages such capacitors typically have over other types of capacitors, for example over capacitors formed from gate oxide. For example, in order to avoid costs associated with a metal-insulator-metal capacitor—such as additional masks and additional wafer processing costs—, it is generally desired to form a capacitor using the multiple layers of routing metal available in any given process.
Metal-to-metal capacitor structures are typically stable, predictable, and provide high-capacitance and low on-chip leakage. Metal-to-metal capacitors also provide better linearity than gate-oxide capacitors, and the quality factor of metal-to-metal capacitors is generally independent of the DC voltage of the capacitor. Such structures, however, oftentimes consume a large area of the IC. In order to reduce the required area, capacitors are many times fabricated as parallel-plate capacitor structures using two or more layers of routing metal in the IC. Accordingly, the capacitors are often designed using multiple layers of stacked, alternately connected metal, which form the opposing electrical nodes of the capacitor.
However, in small geometry processes, the fringe-capacitance between metal lines within the same metal layer can be large, and offers an alternate method for constructing metal-to-metal capacitors. It is generally possible to control the spacing between the metal lines within the same metal layer through accurate lithography. In contrast, the capacitance between the various metal layers may not be as effectively controlled, since the thickness of the field-oxide region in the corresponding metal-‘field-oxide’-metal structure can generally vary from lot to lot and across a die/wafer. Thus, using the fringe-capacitance between metal lines within the same metal layer to construct metal-to-metal capacitors offers notable advantages.
For example, in switched capacitor circuits, it has generally been desirable to design a well matched capacitor in order to obtain high accuracy. Typically, the goal has been to maximize capacitive density in order to minimize the die area occupied by the capacitor, and to minimize the ‘top-plate’-to-substrate capacitance in order to avoid electric charge being drained from critical nodes of the system through parasitic capacitance. In other words, it is oftentimes desirable to create very accurately matched, high capacitance density capacitors without paying the additional cost of parallel-plate capacitors that may be available in a given fabrication process. A minimal ‘top-plate’-to-substrate capacitance is preferable because such a capacitance can be a source of errors in switched capacitor circuits. In most current fringe-capacitance solutions, the top plate is shielded using the metal layer closest to the substrate (or bottom metal layer), hence eliminating the ‘top-plate’-to-substrate capacitance. This, however, reduces the capacitance density of the fringe-capacitance, since the bottom metal layer cannot be used when forming the desired fringe-capacitance.
Many other problems and disadvantages of the prior art will become apparent to one skilled in the art after comparing such prior art with the present invention as described herein.